The present invention relates to a microcomputer for performing interrupt processing and an interrupt control method of a microcomputer, in particular, to a register data saving method in the interrupt processing.
In recent years, a microcomputer has been used in various electronic equipments including mobile electronic equipment such as portable phones, home use appliances, and electronic control devices for automobiles. With higher performances of such electronic equipment and computers, further improvement of processing capability of the microcomputer is demanded.
In a processor of the microcomputer, when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed. When interrupt processing is started, the processor temporarily saves in a stack memory, the data of a program status word (PSW) and a program counter (PC) and data of general purpose registers (context). After completion of the interrupt processing, the saved context can be returned to the PSW, the PC and the general purpose registers so as to restart the interrupted processing.
FIGS. 1A and 1B are block diagrams showing a configuration of a circuit related to the interrupt processing of a microcomputer according to a conventional example. Referring to FIGS. 1A and 1B, the interrupt processing according to the conventional example will be described in detail.
The microcomputer according to the conventional example includes an interrupt controller 100, a processor 200, an instruction memory 300 and a data memory 400. According to an inputted interrupt signal, the interrupt controller 100 sends an interrupt vector INTVCT and an interrupt request INTREQ to the processor 200. At this time, the interrupt controller 100 refers to a priority level PR set for every interrupt signal and outputs the interrupt vector IVCT with a higher priority level PR to the processor 200.
When the interrupt request INTREQ is set to “1”, the processor 200 reads an instruction corresponding to the interrupt vector INVCT from the instruction memory 300 and executes the instruction. At this time, the processor 200 interrupts processing being executed and saves data (context) held by a register file 204 in the processing into the data memory 400.
In detail, the processor 200 includes an interrupt processing control circuit 201, an instruction fetch control circuit 202, an instruction executing section 203 and the register file 204. The interrupt processing control circuit 201 controls the execution of the interrupt processing as well as notifies acceptance of a request of the interrupt processing and completion of the interrupt processing to the interrupt controller 100. In response to an interrupt request INTREQ, the interrupt processing control circuit 201 controls the instruction fetch control circuit 202 to fetch the instruction corresponding to the interrupt vector INVCT. The instruction executing section 203 executes the instruction fetched by the instruction fetch control circuit 202 for the interrupt processing.
When starting the interrupt processing, the instruction executing section 203 saves data of the register file 204 in the data memory 400 (for example, a stack memory). Specifically, the instruction executing section 203 first saves data of the PC and the PSW into the data memory 400 and then, saves data of general purpose registers R0 to R31 into the data memory 400. When saving of the data of register file 204 is completed, the instruction executing section 203 executes processing corresponding to the interrupt request.
When ending the interrupt processing, the instruction executing section 203 returns the data saved into the data memory 400 into the register file 204 in response to a return instruction, and restarts the interrupted processing.
By saving the data of register file 204 and executing the interrupt processing, the interrupt processing can be executed by use of any general purpose registers without destroying the data of register file 204.
A range of the general purpose registers to be used in the interrupt processing is sometimes predetermined depending on data of the interrupt processing. However, in the conventional example, because the general purpose registers to be used in the interrupt processing cannot be designated, it is necessary to always designate all the registers having possibilities of use in the interrupt processing irrespective of data of the interrupt processing. For example, when the general purpose registers to be used in first interrupt processing are registers R0 to R4 and the general purpose registers to be used in second interrupt processing are registers R10 to R14, it is necessary to save data of the registers R0 to R4 and R10 to R14, even if the interrupt processing to be executed is the first interrupt processing. In this case, time taken to save the data of the registers R10 to R14 and a capacity of the memory used for saving are wasteful.
As described above, in the interrupt processing according to the conventional example, since the same registers are used for different interrupt factors, even data of the registers unnecessary to be saved are saved. For this reason, the time necessary for register data saving increases and a memory region necessary for the saving is required to be increased. Especially, as a frequency of interrupt processing increases, the register data saving takes a long time, to cause reduction in processing capability of a program.
In Patent literature 1, by providing a register usage identifier for identifying a register group used by a user program and designating saved registers based on the register usage identifier, the registers to be saved for the interrupt processing are determined. Thereby, the registers to be saved for the interrupt processing can be changed for each user program, so that time necessary for saving and return and a capacity of the memory used for saving are not wasted.